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High-k at 45nm standards – be!

Sematech Consortium of Semiconductor Manufacturers Announces Reaching New Carrier Mobility in Transistors Using High-K Dielectrics (High Dielectric Constants) Under Metal Gates. Sematech expects recent advances to enable high-k dielectrics to be used in CMOS processes in compliance with 45nm regulations.

Recall that until recently the favorite material used as a dielectric in field-effect transistors was silicon dioxide (quartz). However, when the size of the transistors was reduced, a number of parasitic effects were found associated with the fact that the leakage current increased, and the capacitance decreased, leading to an increase in the influence of charge fluctuations on the conductivity of the transistor. Dielectrics with high dielectric constant allow for greater insulating layer thickness with the same or higher gate capacitance.

Compounds of metal oxides with hafnium are among the most likely candidates for implementation as a high-k material. However, the problems of integrating such materials into the production process have not yet been resolved.

Therefore, Sematech’s report on the use of titanium nitride (TiN) as a gate material on a layer of hafnium silicate (HfSiO) insulator gives hope that these problems can be solved in the foreseeable future. It is argued that the mobility of charge carriers in a gate with a thickness of about 10 angstroms is 90% of the mobility of charge carriers on the universal mobility curve determined for quartz.
Carrier thickness and mobility comply with 45nm ITRS (International Technology Roadmap for Semiconductors) specifications.